View MB95F146SPFM_1390282.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds07-12608-2e fujitsu semiconductor data sheet copyright?2006-2007 fujitsu limited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 8-bit proprietary microcontrollers cmos f 2 mc-8fx mb95140 series mb95f146s/f146w/fv100d-101 description the mb95140 series is general-purpose, single-chip micr ocontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. note : f 2 mc is the abbreviation of fujitsu flexible microcontroller. feature ? f 2 mc-8fx cpu core instruction set optimized for controllers multiplication and division instructions 16-bit arithmetic operations bit test branch instruction bit manipulation instructions etc. ? clock main clock main pll clock sub clock (for dual clock product) sub pll clock (for dual clock product) (continued)
mb95140 series 2 (continued) ? timer 8/16-bit compound timer 2 channels 8/16-bit ppg 2 channels 16-bit ppg timebase timer watch prescaler (for dual clock product) ? lin-uart full duplex double buffer clock asynchronous (uart) or clock synchronous (sio) serial data transfer capable ? uart/sio full duplex double buffer clock asynchronous (uart) or clock synchronous (sio) serial data transfer capable ? external interrupt interrupt by edge detection (rising, falling, or both edges can be selected) can be used to recover from lo w-power consumption (standby) modes. ? 8/10-bit a/d converter 8-bit or 10-bit resolution can be selected. ? low-power consumption (standby) mode stop mode sleep mode watch mode (for dual clock product) timebase timer mode ? i/o port the number of maximum ports ? single clock product : 24 ports ? dual clock product : 22 ports port configuration ? general-purpose i/o ports (cmos) : single-clock product : 24 ports : dual-clock product : 22 ports ? flash memory security function protects the content of flash me mory (flash memory device only)
mb95140 series 3 product lineup (continued) part number *1 parameter mb95f146s mb95f146w type flash memory product rom capacity 32k bytes ram capacity 1k byte reset output no option clock system single clock dual clock low voltage detection reset no cpu functions number of basic instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8, and 16 bits minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 mhz) interrupt processing time : 0.6 s (at machine clock frequency 16.25 mhz) peripheral functions general purpose i/o ports single clock product : 24 ports d ual clock product : 22 ports timebase timer interrupt cycle : 0.5 ms, 2.1 ms, 8. 2 ms, 32.8 ms (at 4 mhz main oscillation clock) watchdog timer reset generated cycle at 10 mhz main oscillation clock : min 105 ms at 32.768 khz sub oscillation clock (for dual clock product) : min 250 ms wild register capable of r eplacing 3 bytes of rom data uart/sio data transfer capable in uart/sio full duplex double buffer, variable data lengt h (5/6/7/8 bits), built-in baud rate generator nrz type transfer format, error detected function lsb-first or msb-first can be selected. clock asynchronous (uart) or clock synchr onous (sio) serial data transfer capable lin-uart dedicated reload timer allowing a wide ra nge of communication speeds to be set. full duplex double buffer. clock asynchronous (uart) or clock synchr onous (sio) serial data transfer capable lin functions available as the lin master or lin slave. 8/10-bit a/d converter (8 channels) 8-bit or 10-bit resolution can be selected.
mb95140 series 4 (continued) *1 : mask rom products are cu rrently under consideration. *2 : embedded algorithm is a trade ma rk of advanced micro devices inc. note : part number of the evaluation device in mb 95140 series is mb95fv100d- 101. when using it, the mcu board (mb2146-301a) is required. part number *1 parameter mb95f146s mb95f146w peripheral functions 8/16-bit compound timer (2 channels) each channel of the timer ca n be used as ?8-bit timer 2 channels? or ?16-bit timer 1 channel?. built-in timer function, pwc function, pwm function, capture function and square wave form output count clock : 7 internal clocks and external clock can be selected. 16-bit ppg pwm mode or one-shot mode can be selected. counter operating clock : 8 selectable clock sources support for external trigger start 8/16-bit ppg (2 channels) each channel of the ppg can be used as ?8-bit ppg 2 channels? or ?16-bit ppg 1 channel?. counter operating clock : 8 selectable clock sources watch counter (for dual clock product) count clock : 4 selectable clock sour ces (125 ms, 250 ms, 500 ms, or 1 s) counter value can be set from 0 to 63. (capabl e of counting for 1 minute when selecting clock source 1 second and se tting counter value to 60) watch prescaler (for dual clock product) 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) external interrupt (12 channels) interrupt by edge detection (rising, fa lling, or both edges can be selected.) can be used to recover from standby modes. flash memory supports automatic progra mming, embedded algorithm tm *2 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of write/erase cycles (minimum) : 10000 times data retention time : 20 years boot block configuration erase can be performed on each block block protection with external programming voltage flash security feature for prot ecting the content of the flash standby mode sleep, stop, watch (for dual clock product), and timebase timer
mb95140 series 5 oscillation stabilization wait time the initial value of the main clock oscillation stab ilization wait time is fixed to the maximum value. the maximum value is shown as follows. packages and corresponding products : available : unavailable oscillation stabilization wait time remarks (2 14 ? 2) /f ch approx. 4.10 ms (at 4 mhz main oscillation clock) part number package mb95f146s mb95f146w mb95fv100d-101 fpt-32p-m21 bga-224p-m08
mb95140 series 6 differences among products and notes on selecting products ? notes on using evaluation products the evaluation product has not only the functions of th e mb95140 series but also those of other products to support software development for mu ltiple series and models of the f 2 mc-8fx family. the i/o addresses for peripheral resources not used by th e mb95140 series are therefore access-b arred. read/write access to these access-barred addresses may cause per ipheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. particularly, do not use word access to odd numbered by te address in the prohibited areas (if these access are used, the address may be read or written unexpectedly). note that the values read from barred addresses ar e different between the evaluation product and the flash memory product. therefore, the value must not be used for program. the evaluation product does not support the functions of so me bits in single-byte registers. read/write access to these bits does not cause hardware malfunctions. the evaluation, and flash memory products are designed to behave completely the same way in terms of hardware and software. ? difference of memory spaces if the amount of memory on the evaluat ion product is different from that of the flash memory product, carefully check the difference in the amount of memory from th e model to be actually used when developing software. for details of memory space, refer to ? cpu core?. ? current consumption for details of current consumption, refer to ? electrical characteristics?. ? package for details of information on each package, refer to ? packages and corresponding products? and ? package dimensions?. ? operating voltage the operating voltage is different among t he evaluation and flash memory products. for details of operating voltage, refer to ? electrical characteristics? ? difference between rst and mod pins the input type of rst and mod pins is cmos input on the flash memory product.
mb95140 series 7 pin assignment (top view) (fpt-32p-m21) * : the pins are general-purpose port in single clock product and sub clock oscillation pin in dual clock product. 24 23 22 20 19 18 21 17 1 2 3 5 6 7 4 8 p62/to10 p63/to11 p64/ec1 pg1/x0a* pg2/x1a* pg0 rst vcc p06/int06/an06/to01 p05/int05/an05/to00 p04/int04/an04/sin p02/int02/an02/sck p01/int01/an01/ppg01 p00/int00/an00/ppg00 p03/int03/an03/sot avss 31 30 28 27 26 29 91011 131415 12 16 p07/int07/an07 p10/ui0 p11/uo0 p13/trg0/adtg p14/ppg0 p60/ppg10 p12/uck0/ec0 p61/ppg11 avcc pf2 pf1 mod x0 x1 pf0 vss 32 25
mb95140 series 8 pin description (continued) pin no. pin name i/o circuit type* function 1 p06/int06/ an06/to01 d general-purpose i/o port. shared with external interrupt input (int05, int06), a/d analog input (an05, an06) and 8/16-bit compound timer ch.0 output (to00, to01). 2 p05/int05/ an05/to00 3 p04/int04/ an04/sin e general-purpose i/o port. shared with external interrupt input (int04), a/d converter analog input (an04) and lin-uart data input (sin). 4 p03/int03/ an03/sot d general-purpose i/o port. shared with external interrupt input (int03), a/d converter analog input (an03) and lin-uart data output (sot). 5 p02/int02/ an02/sck d general-purpose i/o port. shared with external interrupt input (int02), a/d converter analog input (an02) and lin-uart clock i/o (sck). 6 p01/int01/ an01/ppg01 d general-purpose i/o port. shared with external interrupt i nput (int00, int01), a/d converter analog input (an00, an01) and 8/16- bit ppg ch.0 output (ppg00, ppg01). 7 p00/int00/ an00/ppg00 8avss ? a/d converter power supply pin (gnd) 9avcc ? a/d converter power supply pin 10 pf2 k general-purpose i/o port. large current port. 11 pf1 12 pf0 13 mod b operating mode designation pin 14 x0 a main clock input oscillation pin 15 x1 main clock i/o oscillation pin 16 vss ? power supply pin (gnd) 17 vcc ? power supply pin 18 pg0 h general-purpose i/o port 19 pg2/x1a h/a this pin is general-purpose port in single clock product (pg2) . this pin is sub clock oscillation pi n in dual clock product (32 khz) . 20 pg1/x0a this pin is general-purpose port in single clock product (pg1) . this pin is sub clock oscillation pi n in dual clock product (32 khz) . 21 rst b? reset pin
mb95140 series 9 (continued) * : for the i/o circuit type, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* function 22 p64/ec1 k general-purpose i/o port. shared with 8/16-bit compound timer ch.1 clock input. 23 p63/to11 general-purpose i/o port. shared with 8/16-bit compound timer ch.1 output. 24 p62/to10 25 p61/ppg11 general-purpose i/o port. shared with 8/16-bit ppg ch.1 output. 26 p60/ppg10 k general-purpose i/o port. shared with 8/16-bit ppg ch.1 output. 27 p14/ppg0 h general-purpose i/o port. shared with 16-bit ppg ch.0 output. 28 p13/trg0/ adtg h general-purpose i/o port. shared with 16-bit ppg ch.0 trigger input (trg0) and a/d trigger input (adtg). 29 p12/uck0/ec0 h general-purpose i/o port. shared with uart/sio ch.0 clock i/o (uck0) and 8/16-bit compound timer ch.0 clock input (ec0). 30 p11/uo0 h general-purpose i/o port. shared with uart/sio ch.0 data output. 31 p10/ui0 g general-purpose i/o port. shared with uart/sio ch.0 data input. 32 p07/int07/ an07 d general-purpose i/o port. shared with external interrupt input (int07) and a/d converter analog input (an07).
mb95140 series 10 i/o circuit type (continued) type circuit remarks a oscillation circuit high-speed side feedback resistance : approx. 1 m ? low-speed side feedback resistance : approx. 24 m ? (evaluation product : approx. 10 m ? ) dumping resistance : approx. 144 k ? (evaluation product : without dumping resistance) b only for input hysteresis input b? hysteresis input d cmos output hysteresis input analog input with pull - up control e cmos output cmos input hysteresis input analog input with pull - up control x0 (x0a) x1 (x1a) n-ch standby control clock input mode input reset input r p-ch n-ch p-ch standby control external control a/d control analog input pull-up control digital output digital output hysteresis input r p-ch n-ch p-ch cmos input standby control a/d control external control analog input pull-up control digital output digital output hysteresis input
mb95140 series 11 (continued) type circuit remarks g cmos output cmos input hysteresis input with pull - up control h cmos output hysteresis input with pull - up control k cmos output hysteresis input r p-ch n-ch p-ch pull-up control standby control digital output digital output hysteresis input cmos input p-ch n-ch r p-ch pull-up control standby control digital output digital output hysteresis input p-ch n-ch standby control digital output digital output hysteresis input
mb95140 series 12 handling devices ? preventing latch-up care must be taken to ensure that maximum vo ltage ratings are not exceeded when they are used. latch-up may occur on cmos ic s if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between v cc pin and v ss pin. when latch-up occurs, power supply current increa ses rapidly and might thermally damage elements. also, take care to prevent the analog power supply voltage (av cc ) and analog input voltage from exceeding the digital power supply voltage (v cc ) when the analog system power supply is turned on or off. ? stable supply voltage supply voltage should be stabilized. a sudden change in power-supply voltage may cause a ma lfunction even within the guaranteed operating range of the v cc power-supply voltage. for stabilization, in principle, keep the variation in v cc ripple (p-p value) in a commercial frequency range (50/60 hz) not to exceed 10 % of the standard v cc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 v/ms during a mome ntary change such as when the power supply is switched. ? precautions for use of external clock even when an external clock is used, oscillation stabilizatio n wait time is required for power-on reset, wake-up from sub clock mode or stop mode. pin connection ? treatment of unused pin leaving unused input pins unconnected can cause abnorma l operation or latch-up, leaving to permanent dam- age. unused input pins should always be pulled up or down through resistance of at least 2 k ? . any unused input/ output pins may be set to output mode and left open, or set to input mode and treat ed the same as unused input pins. if there is unused output pin, make it to open. ? treatment of power supply pins on a/d converter connect to be av cc = v cc and av ss = v ss even if the a/d converter is not in use. noise riding on the av cc pin may cause accuracy degradation. so, connect approx. 0.1 f ceramic capacitor as a bypass capacitor between av cc and av ss pins in the vicinity of this device. ? power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission le vel, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a cerami c bypass capacitor of approximately 0.1 f between v cc and v ss pins near this device.
mb95140 series 13 ? mode pin (mod) connect the mod pin directly to v cc or v ss pins. to prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mod pin to v cc or v ss pins and to provide a low-impedance connection. ? analog power supply always set the same potential to av cc and v cc pins. when v cc > av cc , the current may flow through the an00 to an07 pins.
mb95140 series 14 programming flash memory microcontrollers using parallel programmer ? supported parallel programmers and adapters the following table lists supported parallel programmers and adapters. note : for information on applicable adapter mode ls and parallel programmers, contact the following: flash support group, inc. tel: +81-53-428-8380 ? sector configuration the individual sectors of flash memory correspond to addresses used for cpu access and programming by the parallel programmer as follows: ? programming method 1) set the type code of the parallel programmer to ?1723e?. 2) load program data to pr ogrammer addresses 18000 h to 1ffff h . 3) programmed by parallel programmer package applicable adapter model parallel programmers fpt-32p-m21 tef110-95f146 af9708 (ver 02.35g or more) af9709/b (ver 02.35g or more) *: programmer addresses are corresponding to cpu addresses, used when the parallel programmer programs data into flash memory. these programmer addresses are used for the parallel pr ogrammer to program or erase data in flash memory. flash memory cpu address programmer address* 32 kbytes 8000 h 18000 h ffff h 1ffff h
mb95140 series 15 block diagram * : the pins are general-purpose port in single clock prod uct and sub clock oscillation pin in dual clock product. p14/ppg0 pf0 to pf2 av cc av ss (p00/an00 to p07/an07) (p01/ppg01) (p02/sck) (p03/sot) (p04/sin) (p05/to00) (p06/to01) (p12/ec0) p12/uck0 p62/to10 p63/to11 p00/int00 to p07/int07 p10/ui0 p64/ec1 rst x0, x1 pg2/(x1a)* pg1/(x0a)* pg0 mod, v cc , v ss p13/trg0/adtg (p00/ppg00) p11/uo0 uart/sio rom ram f 2 mc-8fx cpu p61/ppg11 p60/ppg10 16-bit ppg 8/16-bit ppg ch.0 8/10-bit a/d converter 8/16-bit ppg ch.1 port port 8/16-bit compound timer ch.0 8/16-bit compound timer ch.1 interrupt control wild register reset control clock control watch prescaler watch counter external interrupt internal bus other pins lin-uart pg0
mb95140 series 16 cpu core 1. memory space memory space of the mb95140 series is 64k bytes and c onsists of i/o area, data area, and program area. the memory space includes special-purpose areas such as t he general-purpose 7 registers and vector table. memory map of the mb95140 series is shown below. memory map 0000 h 00 8 0 h 0100 h 0200 h 0f 8 0 h 1000 h ffff h extended i/o ram 3 .75 k b yte s mb95fv100d-101 i/o 0000 h 00 8 0 h 0100 h 0200 h 04 8 0 h 0f 8 0 h 1000 h ffff h mb95f146 s mb95f146w i/o ram 1 k b yte extended i/o 8 000 h fl as h memory 3 2 k b yte s regi s ter acce ss prohi b ited regi s ter fl as h memory 60 k b yte s acce ss prohi b ited
mb95140 series 17 2. register the mb95140 series has two types of registers; dedicat ed registers in the cpu and general-purpose registers in the memory. the dedicated registers are as follows: the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and a direct bank pointer (dp) and the lower 8 bits for use as a condition code register (ccr) . (refer to the diagram below.) program counter (pc) : a 16-bit register to indi cate locations where instructions are stored. accumulator (a) : a 16-bit register for temporary st orage of arithmetic oper ations. in the case of an 8-bit data processing instruction, the lower 1 byte is used. temporary accumulator (t) : a 16-bit register which pe rforms arithmetic operations with the accumulator. in the case of an 8-bit data processing instruction, the lower 1 byte is used. index register (ix) : a 16-bit register for index modification extra pointer (ep) : a 16-bit pointer to point to a memory address. stack pointer (sp) : a 16-bit regi ster to indicate a stack area. program status (ps) : a 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register pc a t ix ep sp ps : program counter 16-bit : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status initial value fffd h 0000 h 0000 h 0000 h 0000 h 0000 h 0030 h ps rp ccr bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 dp2 dp1 dp0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r4 r3 r2 r1 r0 h i il1 il0 n z v c dp ? structure of the program status
mb95140 series 18 the rp indicates the address of the register bank cu rrently being used. the relati onship between the content of rp and the real address conforms to the conversion rule illustrated below: the dp specifies the area for mapping instructions (16 di fferent instructions such as mov a, dir) using direct addresses to 0080 h to 00ff h . the ccr consists of the bits indicating arithmetic operat ion results or transfer data contents and the bits that control cpu operations at interrupt. direct bank pointer (dp2 to dp0) specified address area mapping area xxx b (no effect to mapping) 0000 h to 007f h 0000 h to 007f h (without mapping) 000 b (initial value) 0080 h to 00ff h 0080 h to 00ff h (without mapping) 001 b 0100 h to 017f h 010 b 0180 h to 01ff h 011 b 0200 h to 027f h 100 b 0280 h to 02ff h 101 b 0300 h to 037f h 110 b 0380 h to 03ff h 111 b 0400 h to 047f h h flag : set to ?1? when a carry or a borrow from bit 3 to bi t 4 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. this flag is for decimal adjustment instructions. i flag : interrupt is enabled when this flag is set to ?1?. in terrupt is disabled when this flag is set to ?0?. the flag is cleared to ?0? when reset. il1, il0 : indicates the level of the interrupt currently enabled. processes an inte rrupt only if its request level is higher than the value indicated by these bits. il1 il0 interrupt level priority 00 0 high low = no interruption 01 1 10 2 11 3 n flag : set to ?1? if the msb is set to ?1? as the result of an arithmetic operation. cleared to ?0? when the bit is set to ?0?. z flag : set to ?1? when an arithmetic operation re sults in ?0?. cleared to ?0? otherwise. v flag : set to ?1? if the complement on 2 overflows as a re sult of an arithmetic operation. cleared to ?0? otherwise. c flag : set to ?1? when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. set to the shift-out va lue in the case of a shift instruction. "0" "0" "0" "0" "0" "0" "0" "1" r4 r 3 r2 r1 r0 b 2 b 1 b 0 a7 a6 a5 a4 a 3 a2 a1 a0 a15 a14 a1 3 a12 a11 a10 a9 a 8 ? rule for conversion of actual addresse s in the general-purpose register area generated address rp upper op code lower
mb95140 series 19 the following general-purpose registers are provided: general-purpose registers: 8-bit data storage registers the general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8- register. up to a total of 32 bank s can be used on the mb95140 series. the bank currently in use is specified by the register bank pointer (rp), and the lower 3 bits of op code indicates the general-purpose register 0 (r0) to general-purpose register 7 (r7). r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 address 100 h 107 h 1ff h 1f8 h bank 31 bank 0 register bank configuration this address = 0100 h + 8 (rp) 32 banks memory area 32 banks (ram area) the number of banks is limited by the usable ram capacitance. 8-bit
mb95140 series 20 i/o map (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ?? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w 1010x011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r xxxxxxxx b 000a h tbtc timebase timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h to 0015 h ? (disabled) ?? 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h to 0027 h ? (disabled) ?? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h pul1 port 1 pull-up register r/w 00000000 b 002e h to 0034 h ? (disabled) ?? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit compound timer 01 cont rol status register 1 ch.0 r/w 00000000 b 0037 h t00cr1 8/16-bit compound timer 00 cont rol status register 1 ch.0 r/w 00000000 b 0038 h t11cr1 8/16-bit compound timer 11 cont rol status register 1 ch.1 r/w 00000000 b 0039 h t10cr1 8/16-bit compound timer 10 cont rol status register 1 ch.1 r/w 00000000 b 003a h pc01 8/16-bit ppg1 control register ch.0 r/w 00000000 b
mb95140 series 21 (continued) address register abbreviation register name r/w initial value 003b h pc00 8/16-bit ppg0 control register ch.0 r/w 00000000 b 003c h pc11 8/16-bit ppg1 control register ch.1 r/w 00000000 b 003d h pc10 8/16-bit ppg0 control register ch.1 r/w 00000000 b 003e h to 0041 h ? (disabled) ?? 0042 h pcnth0 16-bit ppg control status r egister (upper byte) ch.0 r/w 00000000 b 0043 h pcntl0 16-bit ppg control status regi ster (lower byte) ch.0 r/w 00000000 b 0044 h to 0047 h ? (disabled) ?? 0048 h eic00 external interrupt circuit control register ch.0/ch.1 r/w 00000000 b 0049 h eic10 external interrupt circuit control register ch.2/ch.3 r/w 00000000 b 004a h eic20 external interrupt circuit control register ch.4/ch.5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch.6/ch.7 r/w 00000000 b 004c h to 004f h ? (disabled) ?? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart reception/transmission data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communicat ion control register r/w 000000xx b 0056 h smc10 uart/sio serial mode cont rol register 1 ch.0 r/w 00000000 b 0057 h smc20 uart/sio serial mode c ontrol register 2 ch.0 r/w 00100000 b 0058 h ssr0 uart/sio serial status register ch.0 r/w 00000001 b 0059 h tdr0 uart/sio serial output data register ch.0 r/w 00000000 b 005a h rdr0 uart/sio serial input data register ch.0 r 00000000 b 005b h to 006b h ? (disabled) ?? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper byte) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower byte) r/w 00000000 b
mb95140 series 22 (continued) address register abbreviation register name r/w initial value 0070 h wcsr watch counter status register r/w 00000000 b 0071 h ? (disabled) ?? 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector writing control register 0 r/w 00000000 b 0074 h swre1 flash memory sector writing control register 1 r/w 00000000 b 0075 h ? (disabled) ?? 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? (mirror of register bank pointer (rp) and direct bank pointer (dp) ) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ?? 0f80 h wrarh0 wild register address setting register (upper byte) ch.0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower byte) ch.0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch.0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper byte) ch.1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower byte) ch.1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch.1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper byte) ch.2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower byte) ch.2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch.2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ?? 0f92 h t01cr0 8/16-bit compound timer 01 cont rol status register 0 ch.0 r/w 00000000 b 0f93 h t00cr0 8/16-bit compound timer 00 cont rol status register 0 ch.0 r/w 00000000 b 0f94 h t01dr 8/16-bit compound timer 01 data register ch.0 r/w 00000000 b 0f95 h t00dr 8/16-bit compound timer 00 data register ch.0 r/w 00000000 b 0f96 h tmcr0 8/16-bit compound timer 00/01 timer mode control register ch.0 r/w 00000000 b 0f97 h t11cr0 8/16-bit compound timer 11 cont rol status register 0 ch.1 r/w 00000000 b
mb95140 series 23 (continued) address register abbreviation register name r/w initial value 0f98 h t10cr0 8/16-bit compound timer 10 cont rol status register 0 ch.1 r/w 00000000 b 0f99 h t11dr 8/16-bit compound timer 11 data register ch.1 r/w 00000000 b 0f9a h t10dr 8/16-bit compound timer 10 data register ch.1 r/w 00000000 b 0f9b h tmcr1 8/16-bit compound timer 10/11 timer mode control register ch.1 r/w 00000000 b 0f9c h pps01 8/16-bit ppg1 cycle setting buffer register ch.0 r/w 11111111 b 0f9d h pps00 8/16-bit ppg0 cycle setting buffer register ch.0 r/w 11111111 b 0f9e h pds01 8/16-bit ppg1 duty setting buffer register ch.0 r/w 11111111 b 0f9f h pds00 8/16-bit ppg0 duty setting buffer register ch.0 r/w 11111111 b 0fa0 h pps11 8/16-bit ppg1 cycle setting buffer register ch.1 r/w 11111111 b 0fa1 h pps10 8/16-bit ppg0 cycle setting buffer register ch.1 r/w 11111111 b 0fa2 h pds11 8/16-bit ppg1 duty setting buffer register ch.1 r/w 11111111 b 0fa3 h pds10 8/16-bit ppg0 duty setting buffer register ch.1 r/w 11111111 b 0fa4 h ppgs 8/16-bit ppg start register r/w 00000000 b 0fa5 h revc 8/16-bit ppg output in version register r/w 00000000 b 0fa6 h to 0fa9 h ? (disabled) ?? 0faa h pdcrh0 16-bit ppg down counter register (upper byte) ch.0 r 00000000 b 0fab h pdcrl0 16-bit ppg down counter register (lower byte) ch.0 r 00000000 b 0fac h pcsrh0 16-bit ppg cycle setting buffer register (upper byte) ch.0 r/w 11111111 b 0fad h pcsrl0 16-bit ppg cycle setting buffer register (lower byte) ch.0 r/w 11111111 b 0fae h pduth0 16-bit ppg duty setting buffer register (upper byte) ch.0 r/w 11111111 b 0faf h pdutl0 16-bit ppg duty setting buffer register (lower byte) ch.0 r/w 11111111 b 0fb0 h to 0fbb h ? (disabled) ?? 0fbc h bgr1 lin-uart baud rate gener ator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate gener ator register 0 r/w 00000000 b 0fbe h pssr0 uart/sio dedicated baud rate generator prescaler selection register ch.0 r/w 00000000 b 0fbf h brsr0 uart/sio dedicated baud rate generator baud rate setting register ch.0 r/w 00000000 b 0fc0 h to 0fc2 h ? (disabled) ?? 0fc3 h aidrl a/d input disable register (lower byte) r/w 00000000 b 0fc4 h to 0fe2 h ? (disabled) ??
mb95140 series 24 (continued) ? r/w access symbols ? initial value symbols note : do not write to the ? (d isabled) ?. reading the ? (disabl ed) ? returns an undefined value. address register abbreviation register name r/w initial value 0fe3 h wcdr watch counter data register r/w 00111111 b 0fe4 h to 0fed h ? (disabled) ?? 0fee h ilsr input level select register r/w 00000000 b 0fef h wicr interrupt pin control register r/w 01000000 b 0ff0 h to 0fff h ? (disabled) ?? r/w : readable/writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95140 series 25 interrupt source table interrupt source interrupt request number vector table address bit name of interrupt level setting register same level priority order (at simultaneous occurrence) upper lower external interrupt ch.0 irq0 fffa h fffb h l00 [1 : 0] high external interrupt ch.4 external interrupt ch.1 irq1 fff8 h fff9 h l01 [1 : 0] external interrupt ch.5 external interrupt ch.2 irq2 fff6 h fff7 h l02 [1 : 0] external interrupt ch.6 external interrupt ch.3 irq3 fff4 h fff5 h l03 [1 : 0] external interrupt ch.7 uart/sio ch.0 irq4 fff2 h fff3 h l04 [1 : 0] 8/16-bit compound timer ch.0 (lower) irq5 fff0 h fff1 h l05 [1 : 0] 8/16-bit compound timer ch.0 (upper) irq6 ffee h ffef h l06 [1 : 0] lin-uart (reception) irq7 ffec h ffed h l07 [1 : 0] lin-uart (transmission) irq8 ffea h ffeb h l08 [1 : 0] 8/16-bit ppg ch.1 (lower) irq9 ffe8 h ffe9 h l09 [1 : 0] 8/16-bit ppg ch.1 (upper) irq10 ffe6 h ffe7 h l10 [1 : 0] (unused) irq11 ffe4 h ffe5 h l11 [1 : 0] 8/16-bit ppg ch.0 (upper) irq12 ffe2 h ffe3 h l12 [1 : 0] 8/16-bit ppg ch.0 (lower) irq13 ffe0 h ffe1 h l13 [1 : 0] 8/16-bit compound timer ch.1 (upper) irq14 ffde h ffdf h l14 [1 : 0] 16-bit ppg ch.0 irq15 ffdc h ffdd h l15 [1 : 0] (unused) irq16 ffda h ffdb h l16 [1 : 0] (unused) irq17 ffd8 h ffd9 h l17 [1 : 0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1 : 0] timebase timer irq19 ffd4 h ffd5 h l19 [1 : 0] watch timer/watch counter irq20 ffd2 h ffd3 h l20 [1 : 0] (unused) irq21 ffd0 h ffd1 h l21 [1 : 0] 8/16-bit compound timer ch.1 (lower) irq22 ffce h ffcf h l22 [1 : 0] flash memory irq23 ffcc h ffcd h l23 [1 : 0] low
mb95140 series 26 electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc av cc v ss ? 0.3 v ss + 4.0 v *2 input voltage* 1 v i v ss ? 0.3 v ss + 4.0 v *3 output voltage* 1 v o v ss ? 0.3 v ss + 4.0 v *3 maximum clamp current i clamp ? 2.0 + 2.0 ma applicable to pins* 4 total maximum clamp current |i clamp | ? 20 ma applicable to pins* 4 ?l? level maximum output current i ol1 ? 15 ma other than pf0 to pf2 i ol2 15 pf0 to pf2 ?l? level average current i olav1 ? 4 ma other than pf0 to pf2 average output current = operating current operating ratio (1 pin) i olav2 12 pf0 to pf2 average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma total average output current = operating current operating ratio (total of pins) ?h? level maximum output current i oh1 ? ? 15 ma other than pf0 to pf2 i oh2 ? 15 pf0 to pf2 ?h? level average current i ohav1 ? ? 4 ma other than pf0 to pf2 average output current = operating current operating ratio (1 pin) i ohav2 ? 8 pf0 to pf2 average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ? ? 100 ma ?h? level total average output current i ohav ? ? 50 ma total average output current = operating current operating ratio (total of pins)
mb95140 series 27 (continued) *1 : the parameter is based on av ss = v ss = 0.0 v. *2 : apply equal potential to av cc and v cc . *3 : v i and vo should not exceed v cc + 0.3 v. v i must not exceed the rating voltage. however, if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4 : applicable to pins : p00 to p07, p1 0 to p14, p60 to p64, pf0 to pf2, pg0 ? use within recommended operating conditions. ? use at dc voltage (current). ? the + b signal is an input signal that exceeds v cc voltage. the + b signal should always be app lied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistanc e should be set so that when the + b signal is applied the input current to the microcontroller pin does not ex ceed rated values, either instant aneously or for prolonged periods. ? note that when the microcontroller drive current is lo w, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the v cc pin, and this affects other devices. ? note that if the + b signal is inputted when the microcontroller powe r supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? sample recommended circuits : warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power consumption pd ? 320 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c p-ch n-ch vcc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb95140 series 28 2. recommended operating conditions (av ss = v ss = 0.0 v) * : the values vary with the operating frequency. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter sym- bol pin name condi- tion value unit remarks min max power supply voltage v cc , av cc ?? 2.3* 3.3 v at normal operating, t a = ? 10 c to + 85 c ?? 2.4* 3.3 at normal operating, t a = ? 40 c to + 85 c ?? 2.6 3.6 mb95fv100d-101 t a = + 5 to + 35 ?? 1.5 3.3 retain status in stop mode operating temperature t a ?? ? 40 + 85 c
mb95140 series 29 3. dc characteristics (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max ?h? level input voltage v ih p04, p10 *1 0.7 v cc ? v cc + 0.3 v at selecting cmos input level v ihs p00 to p07, p10 to p14, p60 to p64, pf0 to pf2, pg0, pg1* 2 , pg2* 2 *1 0.8 v cc ? v cc + 0.3 v hysteresis input v ihm rst , mod ? 0.8 v cc ? v cc + 0.3 v hysteresis input ?l? level input voltage v il p04, p10 *1 v ss ? 0.3 ? 0.3 v cc v at selecting cmos input level (hysteresis input) v ils p00 to p07, p10 to p14, p60 to p64, pf0 to pf2, pg0, pg1* 2 , pg2* 2 *1 v ss ? 0.3 ? 0.2 v cc v hysteresis input v ilm rst , mod ? v ss ? 0.3 ? 0.2 v cc v hysteresis input ?h? level output voltage v oh1 output pin other than pf0 to pf2 i oh = ? 4.0 ma 2.4 ?? v v oh2 pf0 to pf2 i oh = ? 8.0 ma 2.4 ?? v ?l? level output voltage v ol1 output pin other than pf0 to pf2 i ol = 4.0 ma ?? 0.4 v v ol2 pf0 to pf2 i ol = 12 ma ?? 0.4 v input leakage current (hi-z output leakage current) i li all input pins 0.0 v < v i < v cc ? 5 ? + 5 a when the pull-up is prohibition setting pull-up resistor r pull p00 to p07, p10 to p14, pg0, pg1* 2 , pg2* 2 v i = 0.0 v 25 50 100 k ? when the pull-up is permission setting power supply current* 3 i cc v cc (external clock operation) f ch = 20 mhz f mp = 10 mhz main clock mode (divided by 2) ? 11.0 14.0 ma at other than flash memory writing and erasing ? 30.0 35.0 ma at flash memory writing and erasing f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ? 17.6 22.4 ma at other than flash memory writing and erasing ? 38.1 44.9 ma at flash memory writing and erasing
mb95140 series 30 (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max power supply current* 3 i ccs v cc (external clock operation) f ch = 20 mhz f mp = 10 mhz main sleep mode (divided by 2) ? 4.5 6.0 ma f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ? 7.2 9.6 ma i ccl f cl = 32 khz f mpl = 16 khz sub clock mode (divided by 2) , t a = + 25 c ? 25 35 a i ccls f cl = 32 khz f mpl = 16 khz sub sleep mode (divided by 2) , t a = + 25 c ? 715 a i cct f cl = 32 khz watch mode main stop mode t a = + 25 c ? 210 a i ccmpll f ch = 4 mhz f mp = 10 mhz main pll mode (multiplied by 2.5) ? 10 14 ma f ch = 6.4 mhz f mp = 16 mhz main pll mode (multiplied by 2.5) ? 16.0 22.4 ma i ccspll f cl = 32 khz f mpl = 128 khz sub pll mode ( multiplied by 4 ) , t a = + 25 c ? 190 250 a i cts f ch = 10 mhz timebase timer mode t a = + 25 c ? 0.64 0.80 ma i cch sub stop mode t a = + 25 c ? 15 a
mb95140 series 31 (continued) (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : p04, p10 can switch the input level to either the ?cmos input level? or ?hysteresis input level?. the switching of the input level can be set by the input level selection register (ilsr). *2 : single clock product only *3 : power supply current is regulated by external clock. ? refer to ?4. ac characteristics (1) clock timing? for f ch and f cl . ? refer to ?4. ac characteristics (2) source clock/machine clock? for f mp and f mpl . parameter sym- bol pin name conditions value unit remarks min typ max power supply current* 3 i a av cc f ch = 10 mhz at operating of a/d conversion ? 1.3 2.2 ma i ah f ch = 10 mhz at stopping of a/d conversion t a = + 25 c ? 15 a input capacitance c in other than av cc , av ss , v cc , v ss f = 1 mhz ? 515pf
mb95140 series 32 4. ac characteristics (1) clock timing (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin name conditions value unit remarks min typ max clock frequency f ch x0, x1 ? 1.00 ? 16.25 mhz when using main oscillation circuit 1.00 ? 32.50 mhz when using external clock 3.00 ? 10.00 mhz main pll multiplied by 1 3.00 ? 8.13 mhz main pll multiplied by 2 3.00 ? 6.50 mhz main pll multiplied by 2.5 3.00 ? 4.06 mhz main pll multiplied by 4 f cl x0a, x1a ? 32.768 ? khz when using sub oscillation circuit ? 32.768 ? khz when using sub pll flash memory product : v cc = 2.3 v to 3.3 v clock cycle time t hcyl x0, x1 100 ? 1000 ns when using main oscillation circuit 50 ? 1000 ns when using external clock t lcyl x0a, x1a ? 30.5 ? s when using sub oscillation circuit, when using external clock input clock pulse width t wh1 t wl1 x0 10 ?? ns when using external clock duty ratio is about 30 % to 70 % . t wh2 t wl2 x0a ? 15.2 ? s input clock rise time and fall time t cr t cf x0, x0a ?? 10 ns when using external clock
mb95140 series 33 t hcyl t wh1 t cr 0.2 v cc x0 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl1 ? input wave form for using external clock (main clock) x0 x1 f ch x0 f ch x1 microcontroller microcontroller c1 c2 ? figure of main clock input port external connection when using a crystal or ceramic oscillator when using external clock open t lcyl t wh2 t cr 0.1 v cc x0a 0.8 v cc 0.8 v cc 0.1 v cc 0.1 v cc t cf t wl2 ? input wave form for using external clock (sub clock) x0a x1a f cl x0a f cl x1a microcontroller microcontroller c1 c2 ? figure of sub clock input port external connection when using a crystal or ceramic oscillator when using external clock open
mb95140 series 34 (2) source clock/machine clock (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : clock before setting division due to machine clock division ratio selection bits (sycc : div1 and div0) . this source clock is divided by the machine clock divi sion ratio selection bits (sycc : div1 and div0) , and it becomes the machine clock. further, the s ource clock can be selected as follows. ? main clock divided by 2 ? pll multiplication of main clock (selec t from 1, 2, 2.5, 4 multiplication) ? sub clock divided by 2 ? pll multiplication of sub clock (select from 2, 3, 4 multiplication) * 2 : operation clock of the microcontroller. machine clock can be selected as follows. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter sym- bol pin name value unit remarks min typ max source clock cycle time* 1 (clock before setting division) t sclk ? 61.5 ? 2000 ns when using main clock min : f ch = 8.125 mhz, pll multiplied by 2 max : f ch = 1 mhz, divided by 2 7.6 ? 61.0 s when using sub clock min : f cl = 32 khz, pll multiplied by 4 max : f cl = 32 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when using main clock f spl ? 16.384 ? 131.072 khz when using sub clock machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 100 ? 32000 ns when using main clock min : f sp = 16.25 mhz, no division max : f sp = 0.5 mhz, divided by 16 7.6 ? 976.5 s when using sub clock min : f spl = 131 khz, no division max : f spl = 16 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.250 mhz when using main clock f mpl 1.024 ? 131.072 khz when using sub clock
mb95140 series 35 f ch (m a in o s cill a tion) f cl ( sub o s cill a tion) divided b y 2 m a in pll 1 2 2.5 4 divided b y 2 sub pll 2 3 4 s clk ( s o u rce clock) clock mode s elect b it ( s ycc: s c s 1, s c s 0) mclk (m a chine clock) divi s ion circ u it 1 1/4 1/ 8 1/16 ? outline of clock generation block
mb95140 series 36 ? operating voltage - operating frequency (when t a = ? 10 c to + 85 c) mb95f146s, mb95f146w ? operating voltage - operating frequency (when t a = ? 40 c to + 85 c) mb95f146s, mb95f146w 131.072 khz 16.384 khz 32 khz 3.3 2.3 16.25 mhz 0.5 mhz 3 . 3 5 mhz 3 mhz 2.7 2. 3 sub pll operation guarantee range source clock frequency (f spl ) operating voltage (v) sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mode operation guarantee range 131.072 khz 16.384 khz 32 khz 3.3 2.4 16.25 mhz 0.5 mhz 3 . 3 2.4 5 mhz 3 mhz 2.7 sub pll operation guarantee range source clock frequency (f spl ) operating voltage (v) sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mode operation guarantee range
mb95140 series 37 ? operating voltage ? operating frequency (t a = + 5 c to + 35 c) mb95fv100d-101 131.072 khz 16.384 khz 3.6 32 khz 2.6 16.25 mhz 10 mhz 0.5 mhz 3 .6 2.6 3 mhz 3 . 3 source clock frequency (f spl ) operating voltage (v) sub pll, sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mode operation guarantee range
mb95140 series 38 [mhz] 16.25 16 15 12 10 7.5 6 5 3 0 3 4 4.062 5 6.4 6.5 8 8 .125 10 [mhz] ? main pll operation frequency machine clock frequency (f mp ) source clock frequency (f sp ) 2.5 2 1 4
mb95140 series 39 (3) external reset (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : refer to ? (2) source clock/machine clock? for t mclk . *2 : oscillation start time of oscillator is the time that the amplitude reaches 90 %. in the crystal oscillator, the oscillation time is between several ms and tens of ms. in ceramic oscillato rs, the oscillation time is between hundreds of s and several ms. in the external clock, the oscillation time is 0 ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns at normal operating oscillation time of oscillator* 2 + 2 t mclk * 1 ? ns at stop mode, sub clock mode, sub sleep mode, and watch mode t r s tl 0.2 v cc r s t 0.2 v cc t r s tl 0.2 v cc 0.2 v cc 2 t mclk r s t x0 ? at normal operating ? at stop mode, sub clock mode, sub sleep mode, watch mode, and power-on internal operating clock internal reset 90 % of amplitude oscillation time of oscillator oscillation stabilization wait time execute instruction
mb95140 series 40 (4) power-on reset (av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) note : sudden change of power supply voltage may acti vate the power-on reset function. when changing power supply voltages during operation, set the slope of rising with in 20 mv/ms as shown below. parameter symbol conditions value unit remarks min max power supply rising time t r ?? 36 ms power supply cutoff time t off ? 1 ? ms waiting time until power-on 0.2 v 0.2 v t off t r 1.5 v 0.2 v v cc v cc 1.5 v v ss hold condition in stop mode limiting the slope of rising within 20 mv/ms is recommended.
mb95140 series 41 (5) peripheral input timing (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int00 to int07, ec0, ec1, trg0/adtg 2 t mclk * ? ns peripheral input ?l? pulse width t ihil 2 t mclk * ? ns t ilih int00 to int07, ec0, ec1, trg0/adtg 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ihil
mb95140 series 42 (6) uart/sio, serial i/o timing (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name conditions value unit min max serial clock cycle time t scyc uck0 internal clock operation output pin : c l = 80 pf + 1ttl. 4 t mclk * ? ns uck uo time t slov uck0, uo0 ? 190 + 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns serial clock ?h? pulse width t shsl uck0 external clock operation output pin : c l = 80 pf + 1ttl. 4 t mclk * ? ns serial clock ?l? pulse width t slsh uck0 4 t mclk * ? ns uck uo time t slov uck0, uo0 0 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns t s cyc t iv s h 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc t s hix t s lov 0. 8 v 2.4 v 0. 8 v 2.4 v uck0 uo0 ui0 0. 8 v t iv s h t s hix t s lov 0.2 v cc 0.2 v cc 0. 8 v cc 0. 8 v cc 2.4 v uck0 uo0 ui0 0. 8 v 0. 8 v cc 0.2 v cc 0.2 v cc 0. 8 v cc t s l s h t s h s l internal shift clock mode external shift clock mode
mb95140 series 43 (7) lin-uart timing sampling at the rising edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 0) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?h? pulse width t shsl sck t mclk * 3 + 95 ? ns sck sot delay time t slove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivshe sck, sin 190 ? ns sck valid sin hold time t shixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95140 series 44 0.8 v 2.4 v t slovi t ivshi t shixi 0.8 v cc 2.4 v 0.8 v sck sot sin t scyc 0.8 v cc 0.2 v cc 0.2 v cc t slove t ivshe t shixe 2.4 v 0.8 v t r t f sck sot sin t slsh t shsl 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode external shift clock mode
mb95140 series 45 sampling at the falling edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 0) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of recept ion data is performed at risi ng edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?l? pulse width t slsh sck t mclk * 3 + 95 ? ns sck sot delay time t shove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivsle sck, sin 190 ? ns sck valid sin hold time t slixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95140 series 46 0.8 v 2.4 v 2.4 v t shovi t ivsli t slixi 2.4 v 0.8 v sck sot sin t scyc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc t shove t ivsle t slixe 2.4 v 0.8 v t f t r sck sot sin t shsl t slsh 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.8 v cc internal shift clock mode external shift clock mode
mb95140 series 47 sampling at the rising edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 1) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of recept ion data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot ? 4 t mclk * 3 ns s ck s ot s in 2.4 v 0. 8 v 0. 8 v t s hovi 2.4 v 0. 8 v 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc 2.4 v 0. 8 v t s cyc t s ovli t iv s li t s lixi
mb95140 series 48 sampling at the falling edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 1) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operating output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot ? 4 t mclk * 3 ns s ck s ot s in 2.4 v 2.4 v 0. 8 v t s lovi 2.4 v 0. 8 v 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc 2.4 v 0. 8 v t s cyc t s ovhi t iv s hi t s hixi
mb95140 series 49 5. a/d converter (1) a/d converter electrical characteristics (av cc = v cc = 1.8 v to 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol value unit remarks min typ max resolution ? ?? 10 bit total error ? 3.0 ? + 3.0 lsb linearity error ? 2.5 ? + 2.5 lsb differential linear error ? 1.9 ? + 1.9 lsb zero transition voltage v ot av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb v 2.7 v av cc 3.3 v av ss ? 0.5 lsb av ss + 1.5 lsb av ss + 3.5 lsb v 1.8 v av cc < 2.7 v full-scale transition voltage v fst av cc ? 3.5 lsb av cc ? 1.5 lsb av cc + 0.5 lsb v 2.7 v av cc 3.3 v av cc ? 2.5 lsb av cc ? 0.5 lsb av cc + 1.5 lsb v 1.8 v av cc < 2.7 v compare time ? 0.6 ? 140 s 2.7 v av cc 3.3 v 20 ? 140 s 1.8 v av cc < 2.7 v sampling time ? 0.4 ?? s 2.7 v av cc 3.3 v external impedance < at 1.8 k ? 30 ?? s 1.8 v av cc < 2.7 v external impedance < at 14.8 k ? analog input current i ain ? 0.3 ? + 0.3 a analog input voltage v ain av ss ? av cc v reference voltage ? av ss + 1.8 ? av cc vav cc pin reference voltage supply current i r ? 400 600 a av cc pin, during a/d operation i rh ?? 5 a av cc pin, at stop mode
mb95140 series 50 (2) notes on using a/d converter ? about the external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the exter nal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore, to satisfy the a/ d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external im pedance so that the sampling time is longer than the minimum value. also, if the sampling time cannot be suff icient, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as |av cc ? av ss | becomes smaller, values of relative errors grow larger. r c analog input note : the values are reference values. ? analog input equivalent circuit rc 2.7 v av cc 3.6 v 1.7 k ? (max) 14.5 pf (max) 1.8 v av cc < 2.7 v 84 k ? (max) 25.2 pf (max) comparator during sampling : on 0 5 10 15 20 25 30 35 40 0 10 20 30 40 50 60 70 80 90 100 01234 0 2 4 6 8 10 12 14 16 18 20 (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ] av cc 1.8 v av cc 2.7 v av cc 2.7 v ? the relationship between external impedance and minimum sampling time
mb95140 series 51 (3) definition of a/d converter terms resolution the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, an alog voltage can be divided into 2 10 = 1024. linearity error (unit : lsb) the deviation between the value along a straig ht line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device a nd the full-scale transition point (?11 1111 1111? ?11 1111 1110?) compared with the actual conversion values obtained. differential linear error (unit : lsb) deviation of input voltage, which is required for ch anging output code by 1 lsb, from an ideal value. total error (unit: lsb) difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. (continued) v fst 1.5 lsb 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 1 lsb 0.5 lsb v ot av ss av cc av ss v nt av cc {1 lsb ( n ? 1 ) + 0.5 lsb} 1 lsb = av cc ? av ss 1024 (v) total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb ideal i/o characteristics total error digital output analog input analog input digital output [lsb] actual conversion characteristic actual conversion characteristic ideal characteristics n : a/d converter digital output value v nt : a voltage at which digital output transits from (n ? 1) to n. =
mb95140 series 52 (continued) v (n + 1) t ? v nt 1 lsb av ss av cc av ss av cc av ss av cc v nt av ss av cc 001 h 002 h 00 3 h 004 h 3 fc h 3 fd h 3 fe h 3 ff h 001 h 002 h 00 3 h 004 h 3 fd h 3 fe h 3 ff h n - 2 h n - 1 h n h n + 1 h { 1 l s b n + v ot } v nt v ( n + 1 ) t full-scale transition error digital output actual conversion characteristic actual conversion characteristic ideal characteristics analog input v fst (measurement value) zero transition error digital output actual conversion characteristic actual conversion characteristic analog input v ot (measurement value) ? 1 differential linear error in digital output n linear error in digital output n v nt ? {1 lsb n + v ot } 1 lsb linearity error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics differential linear error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics v fst (measurement value) v ot (measurement value) n : a/d converter digital output value v nt : a voltage at which digital output transits from (n ? 1) to n. v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = av cc ? 1.5 lsb [v] ideal characteristics = =
mb95140 series 53 6. flash memory program/erase characteristics *1 : t a = + 25 c, v cc = 3.0 v, 10000 cycles *2 : t a = + 85 c, v cc = 2.7 v, 10000 cycles *3 : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . parameter value unit remarks min typ max chip erase time ? 1* 1 1.5* 2 s excludes 00 h programming prior erasure. byte programming time ? 32 3600* 2 s excludes system-level overhead time. program/erase cycle 10000 ?? cycle power supply voltage at program/erase 2.7 ? 3.3 v flash memory data retention time 20* 3 ?? year average t a = + 85 c
mb95140 series 54 mask option * : low voltage detection reset and clock supervisor are options of 5-v products. no. part number mb95f146s mb95f146w mb95fv100d-101 specifying procedure setting disabled setting disabled setting disabled 1 clock mode select* ? single-system clock mode ? dual-system clock mode single-system clock mode dual-system clock mode changing by the switch on mcu board 2 low voltage detection reset* ? with low voltage detection reset ? without low voltage detection reset no no no 3 clock supervisor* ? with clock supervisor ? without clock supervisor no no no 4 selection of oscillation stabilization wait time ? selectable the initial value of main clock oscillation stabilization wait time fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch
mb95140 series 55 ordering information part number package MB95F146SPFM mb95f146wpfm 32-pin plastic lqfp (fpt-32p-m21) mb2146-301a (mb95fv100d-101pbt) mcu board () 224-pin plastic pfbga (bga-224p-m08)
mb95140 series 56 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 3 2-pin pl as tic lqfp le a d pitch 0. 8 0 mm p a ck a ge width p a ck a ge length 7 7 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max code (reference) p-lqfp 3 2-7 7-0. 8 0 3 2-pin pl as tic lqfp (fpt- 3 2p-m21) (fpt- 3 2p-m21) c 2002 fujit s u limited f 3 20 3 2 s -c- 3 -5 7.000.10(.276.004) s q 0. 8 0(.0 3 1) 0.20(.00 8 ) m .059 ?.004 +.00 8 ?0.10 +0.20 1.50 "a" 0.10(.004) 9.000.20(. 3 54.00 8 ) s q 1 8 17 24 9 16 25 3 2 0. 3 20.05 (.01 3 .002) 0.1450.055 (.0057.0022) index 0.500.20 (.020.00 8 ) 0~ 8 ? 0.600.15 (.024.006) 0.25(.010) 0.100.10 (.004.004) ( s t a nd off) (mo u nting height) det a il s of "a" p a rt 0.10(.004) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb95140 series 57 main changes in this edition (continued) page section change results ?? preliminary data sheet data sheet ?? changed the part number mb95fv100b-101 mb95fv100d-101 3 product lineup cpu functions minimum instruction execution time : 0.1 s (at machine clock frequency 10 mhz) minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 mhz) interrupt processing time : 0.9 s (at machine clock frequency 10 mhz) interrupt processing time : 0.6 s (at machine clock frequency 16.25 mhz) 4 added the description flash memory 27 electrical characteristics 1. absolute maximum ratings changed under the table*3; v i1 v i 28 2. recommended operating conditions changed the min value of power supply voltage v cc , av cc . t a = ? 10 c to + 85 c 1.8 2.3 t a = ? 40 c to + 85 c 2.0 2.4 29, 30 3. dc characteristics moved ?h? level input voltage a nd ?l? level input voltage from the section "2. recommended operating conditions". added to f mp = 16 mhz in the section of i cc , i ccs , i ccmpll of power supply voltage. changed the typ and max values of i cts 0.4 0.64 (typ value) 0.5 0.80 (max value) 32 4. ac characteristics (1) clock timing changed the max values of clock frequency x0, x1. when using main oscillation circuit 10 16.25 when using external clock 20 32.50 main pll multiplied by 2 : 5 8.13 main pll multiplied by 2.5 : 4 6.50 added the main pll multiplied by 4 34 (2) source clock/machine clock changed source clock cycle time (when using main clock) min : f ch = 10 mhz, pll multiplied by 1 min : f ch = 8.125 mhz, pll multiplied by 2 changed the max value of source clock frequency f sp . 10 16.25 changed machine clock cycle time (when using main clock) min : f sp = 10 mhz min : f sp = 16.25 mhz changed the max value of machine clock frequency f mp . 10 .000 16.250
mb95140 series 58 (continued) the vertical lines marked in the left side of the p age show the changes. page section change results 35 4. ac characteristics (2) source clock/machine clock changed the diagram of ? outline of clock generation block 36, 37 changed the diagram of ? operating voltage - operating frequency 38 changed the diagram of ? main pll operation frequency range. 49 5. a/d converter (1) a/d converter electrical characteristics changed the pin name in the value section of full-scale transition voltage; avr av cc 55 ordering information the part number is revised as follows; mb2146-301 mb2146-301a
mb95140 series f0701 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

▲Up To Search▲

Price & Availability of MB95F146SPFM

	To Download MB95F146SPFM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .